Please use this identifier to cite or link to this item: https://elib.vku.udn.vn/handle/123456789/4013
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dc.contributor.authorTruong, Quang Dang-
dc.contributor.authorDuong, Ngoc Phap-
dc.contributor.authorLee, Hanho-
dc.date.accessioned2024-07-30T08:52:40Z-
dc.date.available2024-07-30T08:52:40Z-
dc.date.issued2024-02-
dc.identifier.issn2169-3536-
dc.identifier.uri10.1109/ACCESS.2024.3370470-
dc.identifier.urihttps://elib.vku.udn.vn/handle/123456789/4013-
dc.descriptionIEEE Access, Vol 12; pp: 32395-32407.vi_VN
dc.description.abstractThe rapid advancement of powerful quantum computers poses a significant security risk to current public-key cryptosystems, which heavily rely on the computational complexity of problems such as discrete logarithms and integer factorization. As a result, CRYSTALS-Dilithium, a lattice-based digital signature scheme with the potential to be an alternative algorithm that can withstand both quantum and classical attacks, has been standardized as ML-DSA after NIST Post-Quantum Cryptography competition. While prior studies have proposed hardware designs to accelerate this cryptosystem, there is room for further optimization in the tradeoff between performance and hardware consumption. This paper addresses these limitations by presenting an efficient low-latency hardware architecture for ML-DSA, leveraging optimized timing schedules for its three main algorithms. The hardware implementation enables runtime switching main operations in ML-DSA with various security levels. We design flexible arithmetic and hash modules tailored for ML-DSA, the most time-consuming submodules and key determinants of the scheme implementation. Combined with efficient operation scheduling to maximize the utilized time of submodules, our design achieves the best latency among FPGA-based implementations, outperforming state-of-the-art works by 1.27 $\sim 2.58\times $ in terms of the area-time tradeoff metric. Therefore, the proposed hardware architecture demonstrates its practical applicability for digital signature cryptosystems in post-quantum era.vi_VN
dc.language.isovivi_VN
dc.publisherIEEEvi_VN
dc.subjectPost-quantum cryptography (PQC)vi_VN
dc.subjectmodule-lattice-based digital signature standard (ML-DSA)vi_VN
dc.subjectcrystals-Dilithiumvi_VN
dc.subjectlattice-based cryptography (LBC)vi_VN
dc.subjectnumber theoretic transform (NTT)vi_VN
dc.titleEfficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standardvi_VN
dc.typeWorking Papervi_VN
Appears in Collections:NĂM 2024

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