High-performance Ascon IP core design for image and video security applications

Abstract

This paper presents a high-performance hardware implementation of the Ascon authenticated encryption algorithm tailored for image and video security applications, particularly in IoT and surveillance systems. The proposed IP core is described in Verilog and synthesized using the Skywater 130nm CMOS technology. Compared to the baseline design, our implementation achieves a 5.83% increase in performance while maintaining hardware efficiency, occupying approximately 19,000 logic gates at an operating frequency of 50 MHz. Power consumption is measured at 124 mW, making the design suitable for low-power embedded systems. These improvements highlight the potential of deploying lightweight cryptographic cores like Ascon in real-time multimedia security pipelines.