Please use this identifier to cite or link to this item:
https://elib.vku.udn.vn/handle/123456789/6280| Title: | Research and Design of a Low-Power Systolic Array IP Core for Tensor Processing on ASIC Technology |
| Other Titles: | Nghiên cứu và thiết kế lõi IP mảng song song công suất thấp cho xử lý tensor trên công nghệ ASIC |
| Authors: | Duong, Ngoc Phap Ly, Huu Loc |
| Keywords: | Design ASIC Technology |
| Issue Date: | Dec-2025 |
| Publisher: | Vietnam-Korea University of Information and Communication Technology |
| Series/Report no.: | KLTN;21CE029 |
| Description: | Graduation thesis of Computer Engineering Technology; 2021 - 2025. |
| URI: | https://elib.vku.udn.vn/handle/123456789/6280 |
| Appears in Collections: | ĐH-Ngành Công nghệ kỹ thuật máy tính (Computer Engineering) |
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